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Handbook

Concepts

Specifications and Requirements

Design Abstractions

Simulation

Synthesis and Netlist Generation

Floorplanning

Placement

Routing

Parasitics Extraction

Verification

GDSII Export

PDK Basics

Tools

OpenROAD

OpenROAD - Floorplanning

OpenROAD - Placement

OpenROAD - CTS & Optimization

OpenROAD - Routing

OpenROAD - GDS Export

OpenROAD - Parasitic Extraction

OpenROAD - Verification

Yosys

Xschem

KLayout

Magic

Digital Flow

Librelane Flow

Installing the LibreLane Flow

Running a LibreLane Flow

Librelane - Steps

Step I — RTL Linting

Step II — Synthesis

Step III — Floorplanning

Step IV — Placement

Step V — Clock Tree Synthesis (CTS) and Optimization

Step VI — Routing

Step VII — Parasitic Extraction

Step VIII — GDS Export

Step IX — Verification

OpenROAD Flow Script

Analog Flow

Mixed-Signal Flow

Tutorials

Blinking Led

Teach-the-Teacher: Open-Source Digital IC Design

Learning Objectives

Course Structure and Teaching Methodologies

Problem-Based Modules

Assessment Guidelines

Additional Resources

Contributing Guide

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Librelane - Steps

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