OpenROAD - Verification

Verification in OpenROAD focuses mainly on timing, antenna, and parasitic validation. These checks ensure that the implemented design meets electrical and timing constraints before exporting the final layout for full physical sign-off.

OpenROAD does not perform full DRC or LVS checks — those require external tools such as Magic, KLayout, and Netgen.

Official documentation:

• OpenROAD Timing Analysis (OpenSTA)
• OpenROAD Parasitic Extraction (OpenRCX)
• OpenROAD Antenna Check & Repair

1. Timing Verification (OpenSTA)

OpenROAD integrates OpenSTA, a static timing analysis engine that validates the design’s setup and hold constraints across all timing paths. It uses the Liberty, SPEF, and SDC files to calculate delays and report violations.

Example

# Load data
read_liberty tech.lib
read_verilog results/top_gatelevel.v
read_def results/routed.def
read_spef results/design.spef
read_sdc constraints.sdc

# Run STA
report_timing
report_worst_slack
check_timing

Key reports:

• report_timing — full path timing analysis
• report_worst_slack — summarizes worst setup/hold slack
• check_timing — detects missing constraints or invalid paths

Reference: OpenSTA README

2. Parasitic Verification (OpenRCX)

OpenRCX performs RC extraction and consistency checks between routed geometry and expected parasitic values. This ensures that the timing engine uses accurate interconnect delays.

extract_parasitics -ext_model_file tech/rcx_rules.json
write_spef results/design.spef

• Confirms completeness of the routing database.
• Generates logs summarizing total resistance and capacitance per layer.
• Flags missing connections or floating nets (if any).

Reference: OpenRCX Documentation

3. Antenna Checks and Repair

During detailed routing, TritonRoute performs antenna verification to detect long metal segments that may damage transistor gates during fabrication. If needed, OpenROAD can automatically insert antenna diodes or reroute nets.

check_antennas
repair_antennas

Outputs:

• antenna.rpt — summary of violations and fixes
• drc.rpt — optional DRC log from the detailed router

Reference: TritonRoute Antenna Checking

4. Power Grid Analysis (Optional)

For designs with defined power networks, OpenROAD can run a basic power connectivity check to ensure all standard cells are tied to VDD/VSS.

analyze_power_grid -net VDD

This command verifies power grid continuity and reports floating or disconnected segments.

Reference: PDN Analysis Documentation

5. What OpenROAD Does Not Verify

OpenROAD is not a complete physical verification tool. It does not perform geometry-based or schematic-matching verification.

Verification Type	Supported by OpenROAD?	External Tool
DRC (Design Rule Check)	❌	Magic, KLayout
LVS (Layout vs. Schematic)	❌	Netgen
ERC (Electrical Rule Check)	❌	Magic, KLayout
Functional Simulation	❌	Ngspice, Verilator, Icarus Verilog

For complete sign-off, the GDS exported from OpenROAD should be validated using these tools and the corresponding PDK rule decks.

6. Outputs Generated by OpenROAD Verification

File	Description
timing.rpt	Timing path and slack analysis
antenna.rpt	Antenna check report
spef	Extracted parasitic data
sdf	Delay annotation for gate-level simulation
rcx.log	RC extraction summary
sta.log	Static timing analysis log

7. Summary of Key Commands

Command	Function
report_timing	Path-based timing report
report_worst_slack	Setup/hold summary
check_timing	Validate timing constraints
extract_parasitics	Generate parasitic network (OpenRCX)
write_spef / write_sdf	Export RC and delay data
check_antennas / repair_antennas	Antenna rule checking
analyze_power_grid	Basic power grid connectivity check

8. External Sign-off Tools

After OpenROAD verification, complete the physical sign-off using:

Stage	Tool	Purpose
DRC / LVS	Magic / KLayout / Netgen	Geometrical and schematic verification
Functional Simulation	Ngspice, Verilator	Logic and analog behavior verification

9. Next Step

After verification, the design is ready for final sign-off using physical verification tools (Magic/KLayout) and schematic comparison (Netgen). These checks ensure the design is manufacturable and matches the intended schematic before tape-out.

See also: {doc}../analog_flows/klayout_drc_lvs {doc}../analog_flows/magic_layout