Learning Objectives

This section defines the main objectives and expected outcomes of the Teach-the-Teacher program for open-source digital IC design.
The program follows a Problem-Based Learning (PBL) method approach, where participants learn by solving realistic design challenges rather than following step-by-step procedures.

Overall Learning Objectives

By the end of this program, participants (teachers) will be able to:

1. Explain the complete digital design flow from RTL to GDSII using open-source tools.
2. Demonstrate synthesis, floorplanning, placement, and routing using Yosys, OpenROAD, or LibreLane.
3. Guide students in developing, simulating, and validating digital designs using Verilator, GTKWave, and Ngspice.
4. Interpret verification reports (DRC, LVS, STA) and explain their significance in the tape-out process.
5. Apply a problem-based learning methodology, creating learning experiences centered on real design problems.
6. Promote open-source design practices, licensing awareness, and community contribution.

Learning Outcomes

The following outcomes are grouped by three complementary dimensions: Conceptual, Practical, and Pedagogical. Each aligns with the stages of the design flow and the problem-based learning process.

Conceptual Outcomes

• Explain the stages and interdependencies of the digital design flow (RTL → GDSII).
• Describe the goals of ../concepts/synthesis, ../concepts/placement, ../concepts/routing, and ../concepts/verification in relation to manufacturability.
• Identify common design challenges and analyze them from a problem-solving perspective.
• Relate analog and mixed-signal extensions to the same design and verification principles.

Practical Outcomes

• Install and configure open-source design environments (Linux, Docker, or Nix).
• Simulate Verilog designs using Verilator or Icarus Verilog.
• Perform logic synthesis using Yosys and interpret synthesis reports.
• Implement physical design using OpenROAD or LibreLane, including placement, routing, and timing analysis.
• Run DRC/LVS checks in Magic or KLayout and interpret verification results.
• Document and present the complete design flow as a reproducible process.

Pedagogical Outcomes

• Design problem-based modules that connect design challenges with conceptual understanding.
• Guide students through independent exploration, simulation, and debugging processes.
• Encourage collaboration and reflection, helping students articulate how they solved each problem.
• Assess both the design outcome and the problem-solving process (analysis, research, testing, reflection).
• Connect students with community resources, open documentation, and collaborative design ecosystems.

These learning objectives emphasize not only technical proficiency but also the ability to teach through exploration, reflection, and authentic engineering problems.